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00009 #nolist
00019 // Discrete I/O Functions: SET_TRIS_x(), OUTPUT_x(), INPUT_x(),
00020
00021
00022
00023
00024
00025 #define PIN_A0 40
00026 #define PIN_A1 41
00027 #define PIN_A2 42
00028 #define PIN_A3 43
00029 #define PIN_A4 44
00030 #define PIN_A5 45
00031
00032 #define PIN_B0 48
00033 #define PIN_B1 49
00034 #define PIN_B2 50
00035 #define PIN_B3 51
00036 #define PIN_B4 52
00037 #define PIN_B5 53
00038 #define PIN_B6 54
00039 #define PIN_B7 55
00040
00041 #define PIN_C0 56
00042 #define PIN_C1 57
00043 #define PIN_C2 58
00044 #define PIN_C3 59
00045 #define PIN_C4 60
00046 #define PIN_C5 61
00047 #define PIN_C6 62
00048 #define PIN_C7 63
00049
00050 #define PIN_D0 64
00051 #define PIN_D1 65
00052 #define PIN_D2 66
00053 #define PIN_D3 67
00054 #define PIN_D4 68
00055 #define PIN_D5 69
00056 #define PIN_D6 70
00057 #define PIN_D7 71
00058
00059 #define PIN_E0 72
00060 #define PIN_E1 73
00061 #define PIN_E2 74
00062
00064 #define FALSE 0
00065 #define TRUE 1
00066
00067 #define BYTE int
00068 #define BOOLEAN short int
00069
00070 #define getc getch
00071 #define fgetc getch
00072 #define getchar getch
00073 #define putc putchar
00074 #define fputc putchar
00075 #define fgets gets
00076 #define fputs puts
00077
00079
00080
00081 #define WDT_FROM_SLEEP 0
00082 #define WDT_TIMEOUT 8
00083 #define MCLR_FROM_SLEEP 16
00084 #define NORMAL_POWER_UP 24
00085
00086
00088
00089
00090
00091
00092 #define RTCC_INTERNAL 0
00093 #define RTCC_EXT_L_TO_H 32
00094 #define RTCC_EXT_H_TO_L 48
00095
00096 #define RTCC_DIV_2 0
00097 #define RTCC_DIV_4 1
00098 #define RTCC_DIV_8 2
00099 #define RTCC_DIV_16 3
00100 #define RTCC_DIV_32 4
00101 #define RTCC_DIV_64 5
00102 #define RTCC_DIV_128 6
00103 #define RTCC_DIV_256 7
00104
00105
00106 #define RTCC_8_BIT 0
00107
00108
00109
00110
00111
00113
00114
00115
00116 #define WDT_18MS 8
00117 #define WDT_36MS 9
00118 #define WDT_72MS 10
00119 #define WDT_144MS 11
00120 #define WDT_288MS 12
00121 #define WDT_576MS 13
00122 #define WDT_1152MS 14
00123 #define WDT_2304MS 15
00124
00126
00127
00128
00129 #define T1_DISABLED 0
00130 #define T1_INTERNAL 0x85
00131 #define T1_EXTERNAL 0x87
00132 #define T1_EXTERNAL_SYNC 0x83
00133
00134 #define T1_CLK_OUT 8
00135
00136 #define T1_DIV_BY_1 0
00137 #define T1_DIV_BY_2 0x10
00138 #define T1_DIV_BY_4 0x20
00139 #define T1_DIV_BY_8 0x30
00140
00142
00143
00144 #define T2_DISABLED 0
00145 #define T2_DIV_BY_1 4
00146 #define T2_DIV_BY_4 5
00147 #define T2_DIV_BY_16 6
00148
00150
00151
00152
00153 #define CCP_OFF 0
00154 #define CCP_CAPTURE_FE 4
00155 #define CCP_CAPTURE_RE 5
00156 #define CCP_CAPTURE_DIV_4 6
00157 #define CCP_CAPTURE_DIV_16 7
00158 #define CCP_COMPARE_SET_ON_MATCH 8
00159 #define CCP_COMPARE_CLR_ON_MATCH 9
00160 #define CCP_COMPARE_INT 0xA
00161 #define CCP_COMPARE_RESET_TIMER 0xB
00162 #define CCP_PWM 0xC
00163 #define CCP_PWM_PLUS_1 0x1c
00164 #define CCP_PWM_PLUS_2 0x2c
00165 #define CCP_PWM_PLUS_3 0x3c
00166 long CCP_1;
00167 #byte CCP_1 = 0x15
00168 #byte CCP_1_LOW= 0x15
00169 #byte CCP_1_HIGH= 0x16
00170 long CCP_2;
00171 #byte CCP_2 = 0x1B
00172 #byte CCP_2_LOW= 0x1B
00173 #byte CCP_2_HIGH= 0x1C
00174
00176
00177
00178
00179
00180 #define PSP_ENABLED 0x10
00181 #define PSP_DISABLED 0
00182
00183 #byte PSP_DATA= 8
00184
00186
00187
00188 #define SPI_MASTER 0x20
00189 #define SPI_SLAVE 0x24
00190 #define SPI_L_TO_H 0
00191 #define SPI_H_TO_L 0x10
00192 #define SPI_CLK_DIV_4 0
00193 #define SPI_CLK_DIV_16 1
00194 #define SPI_CLK_DIV_64 2
00195 #define SPI_CLK_T2 3
00196 #define SPI_SS_DISABLED 1
00197
00198 #define SPI_SAMPLE_AT_END 0x8000
00199 #define SPI_XMIT_L_TO_H 0x4000
00200
00202
00203
00204
00205 #define NO_ANALOGS 0x86 // None
00206 #define ALL_ANALOG 0x80 // RA0 RA1 RA2 RA3 RA5 RE0 RE1 RE2 Ref=Vdd
00207 #define ANALOG_RA3_REF 0x81 // RA0 RA1 RA2 RA5 RE0 RE1 RE2 Ref=RA3
00208 #define A_ANALOG 0x82 // RA0 RA1 RA2 RA3 RA5 Ref=Vdd
00209 #define A_ANALOG_RA3_REF 0x83 // RA0 RA1 RA2 RA5 Ref=RA3
00210 #define RA0_RA1_RA3_ANALOG 0x84 // RA0 RA1 RA3 Ref=Vdd
00211 #define RA0_RA1_ANALOG_RA3_REF 0x85 // RA0 RA1 Ref=RA3
00212
00213 #define ANALOG_RA3_RA2_REF 0x88 // RA0 RA1 RA5 RE0 RE1 RE2 Ref=RA2,RA3
00214 #define ANALOG_NOT_RE1_RE2 0x89 // RA0 RA1 RA2 RA3 RA5 RE0 Ref=Vdd
00215 #define ANALOG_NOT_RE1_RE2_REF_RA3 0x8A // RA0 RA1 RA2 RA5 RE0 Ref=RA3
00216 #define ANALOG_NOT_RE1_RE2_REF_RA3_RA2 0x8B // RA0 RA1 RA5 RE0 Ref=RA2,RA3
00217 #define A_ANALOG_RA3_RA2_REF 0x8C // RA0 RA1 RA5 Ref=RA2,RA3
00218 #define RA0_RA1_ANALOG_RA3_RA2_REF 0x8D // RA0 RA1 Ref=RA2,RA3
00219 #define RA0_ANALOG 0x8E // RA0
00220 #define RA0_ANALOG_RA3_RA2_REF 0x8F // RA0 Ref=RA2,RA3
00221
00222 #define ADC_OFF 0
00223 #define ADC_CLOCK_DIV_2 1
00224 #define ADC_CLOCK_DIV_8 0x41
00225 #define ADC_CLOCK_DIV_32 0x81
00226 #define ADC_CLOCK_INTERNAL 0xc1
00227
00229
00230
00231
00232
00233 #define L_TO_H 0x40
00234 #define H_TO_L 0
00235
00236 #define GLOBAL 0x0BC0
00237 #define INT_RTCC 0x0B20
00238 #define INT_RB 0x0B08
00239 #define INT_EXT 0x0B10
00240 #define INT_AD 0x8C40
00241 #define INT_TBE 0x8C10
00242 #define INT_RDA 0x8C20
00243 #define INT_TIMER1 0x8C01
00244 #define INT_TIMER2 0x8C02
00245 #define INT_CCP1 0x8C04
00246 #define INT_CCP2 0x8D01
00247 #define INT_SSP 0x8C08
00248 #define INT_PSP 0x8C80
00249 #define INT_BUSCOL 0x8D08
00250 #define INT_EEPROM 0x8D10
00251 #define INT_TIMER0 0x0B20
00252
00253 #list