00001 /*------------------------------------------------------------------------------- 00002 * Project: KoreBot Library 00003 * $Author: flambercy $ 00004 * $Date: 2006/01/26 14:50:58 $ 00005 * $Revision: 1.2 $ 00006 * 00007 * 00008 * $Header: /home/cvs/libkorebot/src/kb_pxa_register.h,v 1.2 2006/01/26 14:50:58 flambercy Exp $ 00009 */ 00010 00022 /* see "Intel PXA27x Processor Family Developer's Manual", pages 1023-1024 00023 Table 24-41. GPIO Controller Register Summary 00024 */ 00025 00026 #define GPIO_BASE 0x40E00000 00027 00028 #define GPLR 0x40E00000 00029 #define GPLR0 (0x40E00000) /* GPIO Pin Level Register GPIO<31:0> */ 00030 #define GPLR1 (0x40E00004) /* GPIO Pin Level Register GPIO <63:32> */ 00031 #define GPLR2 (0x40E00008) /* GPIO Pin Level Register GPIO <95:64> */ 00032 #define GPLR3 (0x40E00100) /* GPIO Pin Level Register GPIO <120:96> */ 00033 00034 #define GPDR 0x40E0000C 00035 #define GPDR0 (0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */ 00036 #define GPDR1 (0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */ 00037 #define GPDR2 (0x40E00014) /* GPIO Pin Direction Register GPIO<95:64> */ 00038 #define GPDR3 (0x40E0010C) /* GPIO Pin Direction Register GPIO<120:96> */ 00039 00040 #define GPSR 0x40E00018 00041 #define GPSR0 (0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */ 00042 #define GPSR1 (0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */ 00043 #define GPSR2 (0x40E00020) /* GPIO Pin Output Set Register GPIO<95:64> */ 00044 #define GPSR3 (0x40E00118) /* GPIO Pin Output Set Register GPIO<120:96> */ 00045 00046 #define GPCR 0x40E00024 00047 #define GPCR0 (0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */ 00048 #define GPCR1 (0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */ 00049 #define GPCR2 (0x40E0002C) /* GPIO Pin Output Clear Register GPIO <95:64> */ 00050 #define GPCR3 (0x40E00124) /* GPIO Pin Output Clear Register GPIO <120:96> */ 00051 00052 #define GRER 0x40E00030 00053 #define GRER0 (0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */ 00054 #define GRER1 (0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */ 00055 #define GRER2 (0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */ 00056 #define GRER3 (0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<120:96> */ 00057 00058 #define GFER 0x40E0003C 00059 #define GFER0 (0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */ 00060 #define GFER1 (0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */ 00061 #define GFER2 (0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<95:64> */ 00062 #define GFER3 (0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<120:96> */ 00063 00064 #define GEDR 0x40E00048 00065 #define GEDR0 (0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */ 00066 #define GEDR1 (0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */ 00067 #define GEDR2 (0x40E00050) /* GPIO Edge Detect Status Register GPIO<95:64> */ 00068 #define GEDR3 (0x40E00148) /* GPIO Edge Detect Status Register GPIO<120:96> */ 00069 00070 #define GAFR 0x40E00054 00071 #define GAFR0_L (0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */ 00072 #define GAFR0_U (0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */ 00073 #define GAFR1_L (0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */ 00074 #define GAFR1_U (0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */ 00075 #define GAFR2_L (0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */ 00076 #define GAFR2_U (0x40E00068) /* GPIO Alternate Function Select Register GPIO<95:80> */ 00077 #define GAFR3_L (0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */ 00078 #define GAFR3_U (0x40E00070) /* GPIO Alternate Function Select Register GPIO<120:112> */ 00079 00080 #define CLK_BASE 0x41300000 00081 00082 #define CKEN 0x41300004 /* Clock enable register */ 00083 00084 #define PWM0_BASE 0x40B00000 00085 00086 #define PWM_CTRL0 0x40B00000 /* PWM0 control register */ 00087 #define PWM_PWDUTY0 0x40B00004 /* PWM0 duty control register */ 00088 #define PWM_PERVAL0 0x40B00008 /* PWM0 Period control register */ 00089 00090 #define PWM1_BASE 0x40C00000 00091 00092 #define PWM_CTRL1 0x40C00000 /* PWM1 control register */ 00093 #define PWM_PWDUTY1 0x40C00004 /* PWM1 duty control register */ 00094 #define PWM_PERVAL1 0x40C00008 /* PWM1 Period control register */